SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4

We present a SystemVerilog-based transmitter (TX) modeling and verification for a universal serial bus 4.0 generation 4 (USB4.0 Gen4). An 11-bit to 7-symbol (11B7S) encoder for three-level pulse amplitude modulation (PAM-3) signaling and a 7:1 serializer were employed to support this encoding. Additionally, a scrambler and current-mode driver were implemented to reduce the jitter caused by the uneven distribution of data levels and for high-speed operation, respectively. SystemVerilog modeling was used to verify the USB4.0 Gen4 TX with a data rate of 40 Gb/s/lane.