Hybrid AI-Optimization Method for Latent Defect Detection Through Test Transistor Insertion in Analog Circuits

This paper shows that latent defects manifesting as pinholes in the gate oxide of transistors, can effectively be detected by inserting extra test transistors in the circuit under test, working in tandem with a neural network test classifier. The test transistors have the functionality of applying specific voltage levels at designated circuit nodes and/or acting as measurement nodes during tests. The optimal test transistor insertion points in the circuit are determined at design time with simulated annealing optimization integrated with a feedback-providing neural network classifier. This hybrid approach is demonstrated in 40nm CMOS for two opamp circuits, showing >90% detection coverage for pinholes below 85% effective thickness.