Signal-Integrity-Aware ILP Routing for Practical 2.5-D Chiplet Interconnects

Chiplet-based designs using 2.5-D advanced packaging offer advantages in cost and flexibility over monolithic system-on-chip (SoC), enabling heterogeneous integration. However, the high interconnect density and stringent signaling requirements, particularly under standards like the Universal Chiplet Interconnect Express (UCIe), present significant routing challenges. Traditional routing methods often struggle with the unique constraints and high escape densities of 2.5-D interposers. This article proposes a signal-integrity (SI)-aware integer linear programming (ILP)-based routing method, specifically tailored for 2.5-D heterogeneous chiplet interconnects adhering to the UCIe standard. Our approach features an ILP formulation for simultaneous escape routing (SER) that integrates layer and track assignment while explicitly optimizing for minimal detours and bends to reduce insertion loss, and incorporating a coupling length constraint to directly mitigate crosstalk. A subsequent area routing stage connects the escape points, ensuring design rule compliance. The experimental results on UCIe-compliant benchmarks demonstrate the effectiveness of our method compared to both an open-source router and a commercial router. Our method not only achieves significant improvements in geometric quality, but also exhibits superior SI, validated through voltage transfer function (VTF) analysis. The proposed method provides an efficient, high-quality solution for routing practical 2.5-D chiplet systems.