Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System

With the increasing complexity of chiplet-based architectures and the growing adoption of heterogeneous computing, efficient and high-precision simulation frameworks are essential for evaluating chiplet interconnect performance. This paper presents an implementation of the UCIe protocol (Universal Chiplet Interconnect Express) within the gem5 simulation environment, providing a comprehensive system-level modeling framework for UCIe-based interconnects. The proposed UCIe link model supports full-stack protocol simulation, including transaction-level processing, die-to-die adaptation, and physical layer interactions. A flit-based packing mechanism is introduced to enable accurate transmission modeling, and an Ack/Nak-based retry mechanism is introduced to ensure robust data integrity. An optimized event-driven scheduling strategy is incorporated to address performance bottlenecks observed in traditional UCIe simulations. Experimental evaluations validate the accuracy and efficiency of the proposed UCIe link model by comparing its latency with theoretical values under different computational workloads. The results show that the model closely matches the theoretical predictions, with a latency deviation of less than 0.5% in most cases. Additionally, performance comparisons between UCIe interconnect, PCIe interconnect, and direct memory transfer reveal that UCIe incurs only a minor protocol overhead (less than 0.7%), making it a practical and scalable solution for multi-chipset interconnects. The proposed UCIe simulation framework provides a high-precision virtual verification platform for chiplet system design, enabling low-cost, high-accuracy performance evaluations, and lays the foundation for future optimizations in large-scale chiplet-based architectures.