TOP: A Combined Logical and Physical Obfuscation Method for Securing Networks-on-Chip Against Reverse Engineering Attacks

The Network-on-Chip (NoC) plays an important role in high-speed and efficient communication in System-on-Chip architectures. However, the NoC topology can be extracted through reverse engineering attacks with the goal of making illegal copies or unauthorized access to interconnect structure and system parameters, including routing protocols and data traffic patterns, thereby posing a threat to the security of the entire system. Simultaneously, the demand for energy efficiency has resulted in the extensive use of power-gating techniques that selectively shut down specific components in the NoC when they are not used to reduce power consumption significantly. This paper introduces TOP, a scalable obfuscation method that can be integrated into power-gating controllers, which aims to fortify the NoC against reverse engineering attacks while providing near-zero additional latency during operation. TOP operates using security keys to assume control of network components and reconfigure its structure and routing paths, utilizing existing units designed for use by power-gating controllers. The mechanism incorporates two distinct obfuscation approaches for strong levels of protection. First, our centralized approach combines power-gating and structure obfuscation, ensuring efficiency and scalability to corrupt the function and traffic pattern of the network when an incorrect key is presented. Second, our distributed approach specifically addresses timing-based attacks by introducing timing violations and triggering malfunctions upon applying wrong key. The scalability, energy efficiency, and minimal latency overhead of TOP, as evidenced by the average power, latency, and PDP overhead results across seven PARSEC programs in five different security levels (1.7-4.3%, 6-14.8%, and 7.8-19.7%, respectively), make it a suitable solution for safety-critical, high-performance, and resource-limited designs.