A Low-Power Backscatter System With a Digitally Controlled Reconfigurable 16-QAM Modulator for Energy-Efficient Wireless Communication

This article introduces a backscatter integrated circuit (IC) designed for 2.4-GHz infrastructure, achieving improved spectral efficiency and throughput at ultra-low power. This is accomplished by: 1) proposing a digital-switch-based frequency-translating 16-QAM modulator to enhance both spectral efficiency and data rate while maintaining robustness against PVT and input power variations; 2) implementing a hardware-efficient architecture that is capable of reconfiguring the modulator seamlessly between BPSK, QPSK, and 16-QAM to comply with multiple wireless standards; and 3) employing a multi-phase ultra-low-voltage phase-locked loop (MP-ULVPLL) to generate a quadrature IF clock with low power. The chip also implemented an energy-detection-based wake-up receiver. Fabricated in 65-nm CMOS, the downlink wake-up receiver consumes $3.2~{\mu }$ W and achieves a sensitivity of −41.7 dBm. The 16-QAM backscatter modulator demonstrates stable error vector magnitude (EVM) performance across various data rates with a constant insertion loss (IL) of ~15 dB over a wide input power range. For data rates up to 200 Mb/s, the worst case EVM of 10.2% occurs at 200 Mb/s with −42-dBm input power, which is still well below the 16-QAM communication standard requirement of 12.5%. The backscatter uplink consumes $15.5~{\mu }$ W at data rates up to 8 Mb/s and less than $19~{\mu }$ W at data rates up to 200 Mb/s, resulting in a best-reported energy efficiency of 0.095 pJ/bit among prior art. The proposed backscatter system is validated in a high-throughput video data streaming prototype. A Wi-Fi communication prototype based on the proposed system has also been developed and validated.