Accelerating Hardware Computational Speed-up of Digital Image Processing Algorithms using Flexible Tunable Multi-NIOS-II Soft Processors on an FPGA: A Centralized Versus a Distributed Solution

These days, there is a big wave of interest in the search for efficient algorithms to solve many problems at the hardware level or embedded systems for measurements and computational intelligence in image processing & understanding in computer vision, as well as the life sciences. There is an interest in hardware architectures showing how FPGAs can compete or perhaps outperform GPUs and CPUs in some applications. Hardware accelerators for a CPU provide power efficiency in the case of FPGAs and computational performance in the case of GPUs with high parallelism. On the one hand, in the case of irregular parallelism, given the latest development in FPGAs, this latter may, in the future, perhaps exhibit superiority over homogeneous parallelism in GPUs. On the other hand, one of the limitations of FPGAs is that they are relatively “hard to program” in an optimized RTL code, which results in a long development time. This paper presents and evaluates a hardware implementation for measurement and application in digital image processing and understanding. We experimentally show the further speed-up obtained by implementing a soft, flexible, and heterogeneous SoC multi-core architecture. This is with some hardware modification via a synchronized varying-size multi-port memory access, with two soft NIOS-II processors, with additional hardware modification, in an FPGA. We experimentally measure the computational performance differences between using a centralized software-programmable SoC approach and a heterogeneous multi-core SoC approach with additional modified hardware. The resulting FPGA system methodology, combining SoC soft and flexible components with additional modified hardware, can be flexibly programmed by combining assembly language, C/C++, and VHDL.