Low-Leakage 8T SRAM Based on Body Effect and Power Gating Technique

Static Random-Access Memory (SRAM) is a fundamental component of memory systems. With the increasing demand for Computing-In-Memory in AI chips and wearable devices, small-size SRAM has become a mainstream technological development. However, as the feature size decreases, leakage current has become one of the primary challenges due to its significant contribution to power consumption. In this paper, we propose body effect and power gating techniques to reduce the leakage current and leakage power of 8T SRAM. The proposed circuit is simulated using a 65nm process with a 900mV supply voltage. First, the leakage characteristics of a single cell are measured and compared at 27°C and 100°C. Compared to the conventional 8T SRAM, the 8T SRAM utilizing body effect and power gating techniques exhibits a 35% reduction in leakage current and power consumption at 27°C and a 46% reduction at 100°C in the hold state. Additionally, the Static Noise Margin (SNM) is improved. Furthermore, a 16×16 read/write circuit was implemented, and simulations at 100°C demonstrated a 22.18% reduction in read power consumption and a 69.95% reduction in write power consumption.