Solution to MSHR contention in multi-core real-time systems based on software hardware collaboration

Multicore processors are widely used in various embedded real-time systems, shared last-level cache (LLC) is an important source of inter-core interference. In order to eliminate interference from LLC, cache partitioning technology divides dedicated cache areas for different cores. However, due to the fact that all cache lines in LLC share a set of miss status holding registers (MSHRs), there exists the MSHR contention problem. In multicore processors, using cache partitioning to achieve LLC space isolation cannot provide predictable cache access times for real-time systems. The existing methods propose dynamically controlling per-core memory-level parallelism (MLP), by limiting the number of MSHRs in each core’s private cache to eliminate MSHR contention in LLC. It is committed to eliminating MSHR contention, but sacrificing per-core MLP will reduce task execution efficiency and decrease private cache throughput. To address the above problem, this paper proposes a novel hardware and operating system collaboration method to eliminate MSHR contention in multicore real-time systems. We add dedicated registers in the cache microarchitecture to perform statistics and direct control of MSHRs in LLC; expand the ARM instruction set to provide privileged instructions for the operating system, enabling it to dynamically allocate the available per-core shared MSHRs during task switching; design a shared MSHR allocation strategy at the LLC level to address MSHR contention while reducing the impact on each core MLP and not wasting LLC MSHRs. This paper evaluates the proposed approach using benchmarks from the EEMBC, SD-VBS, and Mibench1.0 test suites. In a set of SDVBS benchmarks, our approach improves the worst-case execution time(WCET) by up to 11% (average 8%) compared to existing methods.