A Wideband Dual-Mode Power Amplifier with Slotline-Based Series-Parallel Combiner in 28-nm Bulk CMOS Technology

This paper presents a wideband dual-mode power amplifier (PA) implemented in a 28 -nm bulk CMOS technology. The PA features a reconfigurable differential 4/8-way power combiner, utilizing a slotline-based series-parallel combiner (SSPC) and shunt switches, which supports two operation modes: high-power mode (HPM) and low-power mode (LPM). In HPM, the PA achieves a 3-dB bandwidth of 27.9 GHz, with saturated output power ($\mathbf{P}_{\text {sat }}$) of $\mathrm{1 8 - 1 9. 3 ~ d B m, 1 - \mathrm { dB } \text { compression power }}$ ($\mathrm{OP}_{1 \mathrm{~dB}}$) of 13.2-15.1 dBm, and maximum power-added efficiency (PAE max) of $20.4-28.0 \%$ over the frequency range of $45-70 \mathrm{GHz}$. In LPM, the 3-dB bandwidth is 30.8 GHz, with $\mathrm{P}_{\text {sat }}$ of $13.6-14.3$ $\mathrm{dBm}, \mathrm{OP}_{1 \mathrm{~dB}}$ of $9.2-10.3 \mathrm{dBm}$, and PAE ${ }_{\text {max }}$ of $12.5-17.1 \%$. At 60 GHz, measurements using a $64-\mathrm{QAM}, 12-\mathrm{Gb} / \mathrm{s}$ signal demonstrate an rms error vector magnitude (EVM) of -25.3 dB, an average PAE (PAE avg) of $5.1 \%$, and an average output power (Pavg) of 10.7 dBm in HPM, and $-27.3 \mathrm{~dB}, 2.9 \%$, and 5.3 dBm, respectively, in LPM.