A High-Performance 3-D Packaging Structure of SiC Power Module for High-Temperature and High-Power-Density Applications

This study is dedicated to applying the vertical-chip-stacking (VCS) packaging structure with an excellent performance to high-temperature (HT) conditions to break through performance bottlenecks of current HT packages (reducing parasitic inductance and thermal resistance). However, the conventional printed circuit board (PCB)-type VCS packaging structure faces worrisome junction-temperature (T_j) differences between high-side and low-side chips and severe thermal stress at HT. Hence, this article proposed an HT-resistant packaging structure with improved performance while inheriting the ultra-low parasitic inductance, common-mode current suppression, and small size of the VCS package. To address the above issues, the high-temperature co-fired ceramic (HTCC) substrate with excellent material properties substitutes PCB as the interposer and thermally connects silicon carbide (SiC) dies and substrates to construct new lateral heat-conduction pathways. An HT-resistant SiC power module based on the HTCC-type structure is designed, fabricated, and tested. Compared with the PCB-type counterpart, lower thermal stress (> 80% ), T_j difference (> 90% ), voltage stresses (50%, thanks to laminated power terminals), oscillations, and thermal resistance (∼80% ) were observed in the simulation and test results. Moreover, a prototype converter was assembled and operated at the T_j of 250 °C to verify its HT continuous operation capacity.