A Stationary Frame Insight for Understanding Frequency-Locked Loop-Based Inertia Emulation Approaches

The frequency-locked loop (FLL) is a standard synchronization structure for a grid-following inverter controlled in the stationary frame. As the emerging grid code requires that this inverter provides the virtual inertia, two common inertia emulation approaches have been reported. One changes the current reference, and the other modifies the internal structure of the FLL, both relying on the estimated frequency derivative. However, the relevant paper has not deeply compared and interpreted the advantages and disadvantages of these two approaches. It is still unclear which approach is better for inertia emulation. When a conventional insight in the synchronous frame is considered, these two approaches seem the same according to their equivalent swing equations. However, this paper will demonstrate that this recognition is inaccurate from a stationary frame insight. This insight shows that they essentially modify the input of the FLL using the same loop forms. When a fair parameter is tuned, their estimated frequency has no significant differences, but the actual frequency in the grid-connected point can be better improved by changing the current reference. This advantage originates from these two inertia emulation approaches having entirely different physical power exchange characteristics. Unfortunately, this advantage also makes changing the current reference more prone to producing transient synchronization instability than changing the internal structure or no loop change under voltage sag. This instability phenomenon is deeply interpreted by analyzing the transient response of frequency derivative. This interpretation further gives a new design consideration to mitigate this instability. Besides, the stationary frame insight discusses the influences of the current loop and direct-current (DC) voltage loop for the inertia emulation approach via changing the current reference. It shows that the low proportional gains of the current loop or the DC-voltage loop will also produce transient synchronization instability problems under voltage sag. Comparative tests are given to validate the claims.