Effective Adders and Multipliers in Image Processing Applications

The demand for efficient image processing techniques has grown significantly in recent years, mainly in cellphones and embedded systems. This has driven the need for low-power arithmetic circuits mainly adders and multipliers, that stands as the integral components of image enhancement algorithms. Low power adder and multiplier are proposed and that is optimized for image enhancement applications. These circuits mainly use approximate computing technique that helps to minimize the power consumed without affecting the processed image quality. The adders and multipliers are tailored for tasks like image contrast enhancement, edge detection, and noise reduction, where minor inaccuracies are permissible. In the first phase of the research, an arithmetic operation was designed and implemented using an approximate computing architecture for image denoising applications. This work focuses on the development and implementation of Dadda and Baugh-Wooley multipliers using 1-bit approximate adders. The proposed multiplier designs with approximate adders were simulated and synthesized on an FPGA platform using Cadence across different technology nodes. Additionally, a Gaussian filter was employed, utilizing the proposed Dadda and Baugh-Wooley multipliers, in approximate adders for the image processing by using image denoising. The approximate adder thus proposed demonstrates the superior performance, achieving minimum power consumption, delay, and area when compared to conventional approximate adders. The results thus produced has minimized power consumption, there is a reduced delay and area. These solutions are particularly suitable for battery-operated devices and real-time image processing offering an improved performance, power efficiency, and image quality.