APB Protocol Verification using UVM Methodology

The Advanced Peripheral Bus (APB) protocol, a widely-used low-power, low-latency communication interface for System-on-Chip (SoC) designs, is implemented and verified in this project through the design and simulation of an APB Master-Slave architecture using Verilog HDL, alongside a comprehensive verification framework employing the Universal Verification Methodology (UVM). The Verilog-based implementation facilitates reliable and efficient data transfer for write and read operations using control signals (PREADY, PSEL, PWRITE, PWDATA, and PRDATA), with the master managing transactions and the slave ensuring accurate data handling. Simulation results confirm protocol compliance, including timing accuracy, data integrity, and system reliability, demonstrating the protocol's balance between performance and simplicity for low- bandwidth peripherals. Concurrently, the UVM-based verification framework, encompassing testbench architecture, transaction modeling, functional coverage, and debugging strategies, effectively detects protocol violations and optimizes verification workflows. This paper provides a robust foundation for integrating APB into SoC environments, ensuring scalability, adherence to standard specifications, and enhanced verification efficiency. This project implements and verifies an optimized APB Master-Slave architecture using Verilog HDL and a UVM-based framework. The design ensures efficient read/write transactions with minimal latency, reduced bus contention, and enhanced throughput. The outcome confirms improved performance and protocol adherence. The UVM-based verification detects protocol violations, ensures functional coverage, and streamlines debugging. Simulation results validate protocol compliance, accuracy, and reliability, making this a scalable and efficient solution for APB integration in SoC environments.