Parallelized CNN Architecture for Handwritten Digit Recognition on FPGA via Verilog Implementation

This research focuses on implementing a Convolutional Neural Network based handwritten digit recognition system on an FPGA (Field Programmable Gate Array), specifically focusing on utilizing the FPGA’s hardware acceleration capabilities. The parallelism and customizability features of the FPGA architecture significantly enhance performance and improves the accuracy compared to traditional CPU’s(Central Processing Unit) and GPU’s(Graphics processing unit). The System is trained on MNIST(Modified National Institute of Standards and Technology) dataset which includes numerous handwritten image samples. The optimized weights are loaded on to the FPGA and used in the neural network layers, such as convolution, max-pooling layer and fully connected, which are implemented using Verilog. The potential use cases include license plate identification, bank check processing ,postal code recognition and handwritten text scanning.