Study and Performance Evaluation of SRAM Cells in 18nm FinFET Technology

This work is crucial for optimizing SRAM design in advanced FinFET technology, addressing the growing need for low-power and high-speed memory in modern applications. By exploring innovative transistor sizing techniques, it enhances performance while maintaining stability across varying conditions. This research evaluates the performance of 6T, 7T, 8T, 9T, and 12T SRAM cells in terms of write/read delays, power consumption, and stability across SS, TT, and FF process corners, temperatures, and voltages. The 12T cell demonstrates superior performance with lower delays and power consumption, making it ideal for high-speed, low-power applications. The study utilized Cadence Virtuoso for circuit design with 18nm FinFET PDKs to analyze power, delay, and stability metrics under realistic conditions.