FPGA Implementation of IEC 61000-4-30 Quasi-Peak meter with CORDIC Algorithm

This paper presents the first FPGA implementation of the IEC 61000-4-30 quasi-peak using a customized CORDIC algorithm to address the computational demands of real-time supraharmonic assessments in the 9–150 kHz range. The design achieves efficient trigonometric computations and vector magnitude evaluations, significantly reducing resource consumption. With a fully pipelined architecture, the implementation delivers a throughput of 333.3 million computations per second, far exceeding IEC 61000-4-30 standard requirements. The proposed solution demonstrates scalability, compatibility with mid-range FPGA devices, and a balance between precision and resource efficiency, making it a practical approach for modern power quality instrumentation aligned with evolving IEC standards.