A DC Rejection Add-On for the Three-Phase Frequency-Fixed DSOGI-PLL

Phase-locked loops (PLLs) are frequency and phase-angle detection systems, which are useful to synchronize converters to the grid. The frequency-fixed dual second-order generalized integrator-PLL (FFDSOGI-PLL) is a three-phase application that has low computational burden, harmonic rejection capability, and is always stable. However, one drawback appears when a dc offset occurs in the supplying voltage. This article provides a simple but effective method for a full dc offset cancellation, while retaining the advantages of the FFDSOGI-PLL like a 20 dB reduction of low-order harmonics and two to six times less execution time compared to other PLL types with dc-rejection capability. Furthermore, the interdependency between phase tracking, disturbance rejection, and execution time will be discussed. In this context, two parameter sets will be presented, enabling a user to choose between fast tracking and high disturbance rejection. The result is a PLL that is applicable to most grid-connected converters like photovoltaic inverters or active power filters.