An Efficient LUT6-Based Montgomery Modular Multiplication Using Radix-16 Booth Method

This paper explores more efficient LUT6-Based multiplier for Montgomery Modular Multiplication (MMM) on FPGA. Firstly, we analyze and compare the LUT6-Cost of multipliers using previous Radix-4/8/16 Booth methods. Based on the LUT6, we propose an improved LUT6-Based Radix-16 Booth method for Coarsely Integrated Operand Scanning (CIOS) MMM. When the value of multiples remains unchanged for a period of time, this method uses LUT6-Based SDP-RAM to store multiples instead of MUX to select, which effectively reduces the LUT6-Cost of Decode. Secondly, we propose a new LUT6-Based CIOS MMM using the proposed method. Finally, we explore the trade-off between area and latency, present an efficient LUT6-Based MMM hardware design (LUT6-MM) to accelerate CIOS MMM. The LUT6-MM is a scalable, parametric, and reconfigurable design, it is implemented on Xilinx Virtex-7 FPGA. When performing 1024/2048-bit MMM, the results show that the area*latency products (ALPs) of LUT6-MM ($w_{1}$ =32, $w_{2}$ =128) are 51.1%/48.8% of the previous state-of-art scalable and parametric LUT6-Based reference (Non-Reconfigurable, Not using DSP).