SFDR Improvement in DDS Using Memory Compression Techniques

Analysis and comparison of different memory compression techniques for Direct Digital Synthesizer (DDS) is presented in this paper. The important parameters of DDS are frequency resolution, number of frequency spots and frequency step size. These parameters are mainly dependant on the minimum phase increment of accumulator. Any improvement in these parameters requires width of the accumulator register to increase. As size of lookup memory grows exponentially with width of the accumulator output and hardware limitations restrict the size of memory which can be allocated for Lookup Table (LUT). To overcome this, accumulator output is truncated to match LUT size. Truncation, however results in generation of spurious signal which reduces Spurious Free Dynamic Range (SFDR). There are some techniques available to compress this memory requirement. In this paper different compression techniques are compared for their performance. We will first be briefly discussing causes of spurious signals in the DDS circuitry and then we will be analyzing various techniques/algorithms employed to minimize these causes to obtain cleaner output in DDS and improve its SFDR.