Design of Adder Circuits using GNRFETs in Ternary Logic

This paper presents the design of ternary adder schematics with graphene nanoribbon field effect transistor (GNRFET). The adder circuits are developed by using the basic, universal and decoder circuits. Thus, the basic, universal and decoder circuits are also developed using GNRFETs. Next, the performances of the presented schematics are equated to conventional CNTFET based circuits. The performances such as delay, power and power delay product (PDP) are analyzed. The industry standard HSPICE simulator is used to design the proposed half adder and full adder circuit and analyze the performances. The HSPICE simulations show that the proposed GNRFET-based adders exhibit a 59.01% average reduction in delay, power and PDP compared to CNTFET implementations.