IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems

Large-area chips using advanced processes are facing challenges in yield rate and limitations in lithographic area. Chiplet technology has emerged as a promising solution with improved flexibility, scalability, and yield rate. However, even if each chiplet is internally deadlock-free, the inter-chiplet network may still encounter deadlock issues. Ensuring the modular design and topology agnostic of each chiplet, while achieving better performance under limited inter-chiplet bandwidth, is the main challenge of routing algorithms. This article introduces IPDR, an inter-chiplet priority-driven deadlock resolution mechanism specifically designed for inter-chiplet networks, where the inter-chiplet link often constitutes a critical system bottleneck. IPDR imposes no restrictions on virtual channel (VC) allocation or turn strategies during normal state, avoiding performance penalties from conservative deadlock avoidance methods. Upon detecting a deadlock at boundary routers, IPDR prioritizes the inter-chiplet traffic by allowing the blocked inbound packet to advance and occupy a dedicated IPDR buffer. The IPDR buffer in each boundary router guarantees that at least one bubble exists in the dependency chain during an inter-chiplet deadlock, thereby breaking the deadlock dependency. To ensure correctness and prevent the formation of new deadlocks during recovery, virtual network (VN) separation rules are enforced throughout the recovery process. This design enables efficient deadlock resolution with minimal performance degradation during recovery state. Moreover, a fine-grained packet packing is implemented in IPDR to improve the bandwidth utilization of small packets. Compared with the state-of-the-art related work, IPDR achieves 7.30%–66.62% latency reduction at the cost of 0.77%–6.98% area overhead.