An Open-Source High-Concurrency and High-Performance Parallel Router for UltraScale FPGAs

With the growth of circuit size and FPGA complexity, routing becomes an increasingly complicated and timeconsuming task for modern FPGAs. To accelerate FPGA routing, many parallel algorithms have been proposed to perform concurrent routing for multiple independent nets that have no overlaps in routing resources. The requirement on net independence can help reduce the synchronization overhead by circumventing the data race in different threads, but it will significantly limit the parallelism due to the large number of overlapping nets in modern circuit designs. Therefore, to strive for large-scale parallelism, it is a promising direction to explore the parallel routing for overlapping nets. In this work, we first propose a parallel overlap-tolerant router, called Potter, including the runtimefirst Potter-R and the stability-first Potter-S. Potter-R employs a partitioning-based recursive net scheduling algorithm to divide nets into balanced groups while minimizing resource overlaps among net groups. These net groups are then routed independently and concurrently. A novel factor updating mechanism is proposed to accelerate solving congestion in the negotiation-based routing algorithm. Furthermore, based on Potter-R, we devise an efficient synchronization strategy in Potter-S to maintain determinism when concurrently routing overlapping nets. An enhanced clustering-based net scheduling method is developed to minimize overlaps among different net groups. In the FPGA24 routing contest benchmarks, our proposed method outperforms the state-of-the-art methods in both running time and wire length. Potter-R not only achieves the largest 12.34× speedup to the sequential router RWRoute but also has the best 4% improvements on wire length. Furthermore, compared with the fastest deterministic parallel router CUFR, Potter-S can