Record PMOS WSe2 GAA Performance Using Contact Planarization, and Systematic Exploration of Manufacturable, High-Yield Contacts

Two-dimensional (2D) transition metal dichalcogenides (TMDs) hold significant promise for both front-end-of-line (FEOL) and back-end-of-line (BEOL) applications. Here, we report new approaches to contact formation in global back gate 2D PMOS transistors using a manufacturable physical vapor deposition (PVD) sputtering process. We present a systematic study of novel sputtered contacts ($\text{Sb} / \text{Pt}, \text{Sb}_{2} \text{Te}_{3}$, $\text{Bi}_{2} \text{Te}_{3}$) to multilayer $\text{WSe}_{2}$ and through statistical analysis we discover trends of increasing performance with Pt thickness and post-metal anneal. Optimized conditions give $\mathrm{R}_{\mathrm{C}}$ down to $1.3 \mathrm{k} \Omega. \mu \mathrm{m}$ at $\mathrm{N}(\text{inv})=1 \mathrm{e} 13 \text{cm}^{-2}$ and $\mathrm{I}_{\mathrm{d}, \max }=212 \mu \mathrm{A} / \mu \mathrm{m}$ at $\mathrm{V}_{\mathrm{d}} =-1 \mathrm{V}$, the highest performance to date using sputtered contacts. Further, we pioneer a new approach to contact-first gate-allaround (GAA) schemes through contact planarization using chemical mechanical polishing (CMP). This first-of-kind CMP flow demonstrates significant performance gains over non-CMP contacts ($4 \times$). CMP Ru contacts to monolayer $\text{WSe}_{2}$ GAA devices achieve record drive currents $>600 \mu \mathrm{A} / \mu \mathrm{m}$ and $\text{SS}=132 \text{mV} / \text{dec}$.