A Temperature-Insensitive Period-Modulation CDC with DLL-Based Comparator Delay Compensation Achieving 53.5ppm/°C without Calibration

This paper presents a temperature-insensitive period-modulation (PM) capacitance-to-digital converter (CDC) with a delay-locked-loop (DLL) based compensation alleviating temperature-dependent comparator delays. Moreover, a half-period alternate-sampling technique is proposed to track the comparator offset and mitigate its variation in a swing-boosted front-end. Our 180nm CMOS prototype achieves 53.5ppm/°C output variation over -40 to 85°C without any calibration or external clock. The conversion achieves the best $\text{FoM}_{\mathrm{w}}$ of 6.0pJ/conv.step among temperature-insensitive PM CDCs.