Orthogonal $\mathbf{V}_{\mathbf{T}}$ Tuning for Oxide Semiconductor 2T Gain Cell Enabled by Interface Dipole Engineering

We demonstrate interface engineering (eng.) of the gate dielectric as an independent knob to tune the threshold voltage $(V_T)$ of Oxide Semiconductor (OS) FETs for twotransistor (2T) gain-cell memories (GC). By leveraging Interface Dipole (ID) eng. for Indium-Tungsten-Oxide (IWO) FETs, we achieve a $\sim 450-500 \text{mV} V_T$ increase compared to the standard $\text{HfO}_2$ (STD), maintaining this $\Delta V_T$ from 8°C to cryogenic temperatures. ID engineered (ID engd.) GCs exhibit good reliability, showing a ~60 mV shift under worst-case DC positive-bias stress (PBS) at 85°C. This approach is demonstrated across other OS such as Indium-Oxide, Indium-Tin-Oxide, and Indium-Gallium-Zinc-Oxide and at short channel lengths (sub-100 nm). Finally, simulations indicate that ID $V_T$ tuning reduces GC refresh energy by $\sim 50,000 \times$ compared to STD, enabling energy-efficient GC.