Novel p-Type Bulk-Inserted Bitline Pad Structure for Efficient Erase Operation in Vertical NAND Flash Memory

We propose a novel vertical nand (VNAND) structure designed to enhance erase performance, incorporating a bitline (BL) pad with an inserted p+ Si region. In contrast to the conventional structure, which utilizes only a gate-induced drain leakage (GIDL) erase scheme, this novel structure directly transfers hole carriers from the inserted p+ bulk region, which serves as an abundant source of holes during erase operations. This approach overcomes the limitations of conventional structures, where expanding the n-type region alone fails to significantly enhance GIDL efficiency during the erase process. Its effectiveness is further amplified as the VNAND stack height increases. Numerical analysis demonstrates significant performance gains in terms of erase time compared to conventional structures.