Design and Modeling of Area & Power Efficient Line Decoders using GDI Technique for SRAM Designs

This research addresses the challenge of high power consumption and suboptimal performance in conventional CMOS decoder designs. To overcome these limitations, a novel CMOS decoder architecture based on the Gate Diffusion Input (GDI) technique is proposed. The GDI method enables efficient realization of basic logic gates using only two transistors, significantly reducing circuit complexity. This technique is employed to design 2-to-4 and 4-to-16 decoders and is compared against existing mixed-logic implementations, including transmission gate logic and dual-value pass-transistor logic. Three variants of the 2-to-4 decoder are developed: a 12-transistor GDI-based design, a 14-transistor low-power (LP) version, and a 15-transistor high-performance (HP) version. Among these, the 12-transistor GDI-based decoder achieves the best results in terms of reduced area and power consumption. Furthermore, a 4-to-16 decoder is constructed using the same GDI approach. Simulation results using EDA tools confirm that the proposed GDI-based designs significantly reduce power usage, enhance performance, and minimize silicon area. These findings establish the proposed decoders as effective solutions for energy-efficient and compact VLSI circuit applications.