Low-Power Clock-Gated PAM4 SerDes Design for High Data Rate Communication System

The architecture of the Serializer/Deserializer (SerDes) proposed in this paper is of low power and configurable, relying on clock gating and four-level pulse amplitude modulation (PAM4) to implement high-speed data transmission up to 112 Gb/s. The proposed design is onto an FPGA to take advantage of both its reconfigurability and hardware acceleration for faster simulation and testing. In particular, clock gating is used here to minimize the dynamic power consumption further by disabling the clock signal selectively to idle flip-flop-based logic blocks. The architecture includes all the essential functional blocks like the PRBS generator/checker, scrambler/descrambler, Gray encoder/decoder, and a simplified Mueller-Muller phase detector designed for PAM4. PAM4 provides higher bandwidth efficiency compared with NRZ-based systems, with two bits transmitted per symbol. The proposed system allows the parameterization of various channels for the study of signal integrity, allowing its use in the verification of equalization and forward error correction (FEC) algorithms. The proposed model synthesized by Verilog HDL for the Xilinx Vivado platform achieves higher power efficiency and performance compared with conventional SerDes designs.