Phase-Locked Loop Applications: A Comparative Analysis of Charge Pump Topologies

This paper designing topologies of charge pumps optimized for ultra-low-voltage, ultra-low-power applications of a Phase-Locked Loop (PLL), where output performance along with power efficiency matters most. Three topologies of CP are analyzed: a clock-controlled charge pump, a symmetric charge pump, and an operational amplifier (op-amp)-based charge pump, both utilizing a 1V supply voltage. It has a minimum power dissipation of 0.48 mW from a symmetric charge pump, while an op-amp-based design has a highest dissipation of 2.01 mW. Analysis of voltage swing depicts that a clock-controlled circuit exhibits a highest operating range of 980–1560 mV, then an op-amp-based (250–480 mV) and a symmetric design follows at a range of 220–500 mV. Current matching performance, required to minimize phase error, varies at 69 µA (symmetric), 20 µA (clock-controlled), and 50 µA (op-amp-based). The result depicts that though an op-amp-based topology offers more voltage swing, a symmetric charge pump provides a more suitable topology for ultra-low-power applications of PLL owing to its energy efficiency along with satisfactory performance.