Deep Learning Based Channel Estimation for Massive MIMO: A Sparsity Adaptive Compressive Sensing Method and FPGA Implementation

Massive multiple-input multiple-output (MIMO) systems face significant overhead due to the surge in the number of antennas, posing notable challenges for hardware implementation. Currently, channel estimation methods that combine Compressed Sensing (CS) with Deep Learning (DL) are developed to address this issue. However, the sparsity adaptation of channel estimation methods is still a huge problem, and Channel State Information (CSI) estimation accuracy still needs improvement. This paper proposes a novel structure combining CS and DL, named the sparsity adaptive deep learning compressed sensing (Sa-DLCS) method, which can leverage sparsity adaptation to obtain globally optimal channel estimation. It includes three key steps: 1) preprocessing, 2) updating the neural network (NN) mapping relation, and 3) postprocessing. First, sparsity adaptation is realized to select matching atoms by taking the arithmetic mean value and the harmonic mean value of the correlation between the received signal and the measurement matrix as the threshold. Second, it updates the NN input-output mapping relationship. Consequently, the NN has a new mapping relationship involving the measurement matrix in the CS. Third, based on the output of the NN, a high-precision channel estimation is employed, where the errors are related to the error size of the inverse of the measurement matrix. Simulation results showed that the proposed methods have better normalized mean square error performance than the existing deep learning based compressed sensing method. This paper also provides the hardware architecture of Sa-DLCS algorithm and discusses the optimization strategies for its hardware implementation on Field-Programmable Gate Array, indicating Sa-DLCS is a hardware-efficient channel estimation algorithm. In addition, we implement Sa-DLCS algorithm on xilinx Virtex-7 FPGA, and compare it with the hardware implementation scheme of advanced compressed sensing based channel estimator. The results show that the proposed Sa-DLCS channel estimation algorithm can reduce the reconstruction time by up to 54% without increasing the FPGA logic resources.