Continuous Flow 4096-Point FFT/IFFT Hardware Architecture for 5G Applications

This paper presents a high-throughput, low-latency 4096-point FFT/IFFT hardware design tailored for 5G applications. Using the radix-16 FFT algorithm, the architecture efficiently supports both FFT and IFFT operations with minimal modifications. It employs only three radix-16 butterfly units constructed from pipelined radix-4 structures to achieve lower operational complexity at higher radix levels. To accommodate real-time application requirements, a continuous flow design is proposed utilizing a Conflict-Free Memory Addressing (CFMA) scheme for data ordering to access various memory banks in parallel. The twiddle factors are generated using Canonical Signed Digit (CSD) and CORDIC architectures, optimizing area and power usage while eliminating the need for ROM units. The design verified both FFT and IFFT operations using MATLAB and synthesized with the Cadence Genus tool in a UMC 65nm process at 250 MHz. It achieves a latency of 2.43 $\mu $ s and a throughput of 4 GS/s, representing a 29.03% increase in throughput compared to the best results reported in the literature, with a Signal-to-Quantization Noise Ratio (SQNR) of 51.2 dB.