A 3× Offset, 2.9× Power, 1.3× Sensing Time, and 4× Area Reduction Direct Input Transfer Offset Cancel DRAM IO Sense Amplifier With Static Current-Free Pre-Sensing

With the increase in memory density and scaling down of the DRAM process, the length of the global IO pairs (GIO and GIOB) and the offset voltage ( $V_{\text {OS}}$ ) have increased. This degrades the power consumption and sensing time ( $t_{\text {SEN}}$ ) of IO sense amplifiers (IOSAs) that sense the differential input voltage via long GIO pairs ( $\Delta V_{\text {GIO}}$ ). Conventional IOSAs use the self-time logic, hybrid IOSA, and GIO switches to reduce the power consumption of IOSA. However, they do not consider $V_{\text {OS}}$ of the IOSA, which requires a larger $\Delta V_{\text {GIO}}$ for robust IOSA sensing operations, increasing $t_{\text {SEN}}$ to develop a large $\Delta V_{\text {GIO}}$ and increasing the power consumption to pre-charge these discharged GIO pairs. To mitigate these issues, offset cancellation (OC)-IOSA has been proposed. However, since two large coupling-capacitor-based OC-IOSAs transfer $\Delta V_{\text {GIO}}$ via capacitive coupling, it suffers from input voltage attenuation, severe area overhead, and static current. This work proposes a single capacitor-based direct input transfer static current-free pre-sensing IOSA (SCFP-IOSA) to reduce $V_{\text {OS}}$ and power consumption with a small area and high speed. The direct input transfer scheme is adopted in SCFP-IOSA, which removes input voltage attenuation and does not require large capacitors, thereby enhancing the sensing margin and relieving area overhead. In addition, a novel static current-free pre-sensing, which uses RC delay exponential nature, is proposed that not only pre-amplifies $\Delta V_{\text {GIO}}$ to enhance $V_{\text {OS}}$ tolerance but also reduces power consumption by removing static current during the pre-sense (PS) operation. The simultaneous coupling down and $\Delta V_{\text {GIO}}$ developing operation also contribute to the fast sensing operation of SCFP-IOSA. According to the measurement on the experimental chip fabricated in a 28-nm CMOS technology, SCFP-IOSA achieves three times lower $\sigma V_{\text {OS}}$ of 4.42 mV, 2.9 times lower power consumption of $2.15~{\mu }$ W, and 1.3 times faster $t_{\text {SEN}}$ of 3.75 ns with 4.46 times smaller area of $10.28~{\mu }$ m² compared with the state-of-the-art OC-IOSA.