Error Correction Codes for Double Burst Errors Correction in Memories

This paper addresses the issue of double burst errors occurring in memories and presents the design of corresponding error correction codes (ECC). The proposed ECCs can correct up to two burst errors simultaneously, each up to 4-bit. The errors’ positions are randomly distributed across any bit within the codeword. The proposed coding scheme is designed with FUEC and syndrome-based decoding. Then the scheme is implemented in hardware with Verilog HDL, utilizing parallel decoding techniques to minimize the latency and parity bits’ number. Comparative evaluations on hardware overheads are conducted for ECCs with the correction capabilities of double burst errors. To minimize the hardware overhead associated with codes with high correction requirements, bit interleaving techniques are applied, further reducing codec area, power, and delay. The ECCs are proved to demonstrate excellent performance in correcting double burst errors, with optimized hardware efficiency.