Design and Analysis of Modified Carry SelectAdder Using Cut-Back Technique For Signal Processing Application

Efficient signal processing applications demand high-speed and low-power arithmetic circuits to handle complex computations. Among various arithmetic units, adders play a pivotal role in determining overall system performance. The Carry Select Adder (CSLA) is widely recognized for its high-speed operation, but it often incurs significant power and area overheads. This paper proposes a Modified Carry Select Adder (M-CSLA) employing the Cut-Back Technique to enhance performance by optimizing power, delay, and area metrics.The proposed design leverages the cut-back technique to minimize redundant operations in the adder's carry generation process, reducing critical path delay and overall power consumption. The optimization focuses on minimizing hardware redundancy by reusing partial computations and streamlining the propagation of carry signals. Extensive simulations werconducted using a standard CMOS technology node, and the results demonstrate a significant improvement in delay and power consumption compared to conventional CSLA designs.This modified adder design is validated for various signal processing applications, such as digital filters and Fast Fourier Transform (FFT) units, showcasing its suitability for real-time processing tasks. The findings indicate that the proposed M- CSLA with the cut-back technique is a viable candidate for future low-power and high-performance VLSI systems.