A Hybrid FPGA-GPU Implementation of CCSDS Image Data Decompression

The CCSDS (Consultative Committee for Space Data Systems) image compression standard, CCSDS 122.0-B-2, is widely used in space applications to optimize data storage and transmission. This paper presents a novel hybrid FPGA-GPU implementation of the CCSDS image decompression algorithm for satellite data processing. The design integrates a Verilog-HDL-based Bit-Plane Decoder on the Altera Arria 10 GX FPGA with a GPU-accelerated Inverse Discrete Wavelet Transform (IDWT) using the CUDA framework. In lossless compression, the absence of a segment byte limit restricts multithreading, making single-threaded performance critical. Our hybrid approach achieves a 3x speedup over software-only decompression. In lossy mode, the segment byte limit allows parallelism, enabling multi-threaded decompression. To utilize this, two FPGA-based engines were deployed, resulting in a 5x improvement over software methods. This hybrid solution supports real-time, low-latency decompression, adheres to CCSDS standards, and significantly reduces satellite image processing turnaround time at ground stations.