Performance Optimized VCO Based Quantizer with Johnson Counter for A CT Sigma Delta ADC

This paper presents design and analysis of low power Current Starved Voltage Controlled Oscillator (CSVCO) enabled Quantizer with and without using Johnson Counter for Continuous Time Sigma Delta Analog to Digital Converter (CTSDADC) using 90nm CMOS technology in Cadence Virtuoso tool. The proposed designs consist of low power 7 stage CSVCO, Johnson Counter, 7 1-bit quantizers using TSPC, Thermometer to Binary Converter and a 3-bit Resistor String DAC. The quantizer is clocked at 50MHz sampling frequency and the frequency of input signal is 100kHz. The supply voltage for both designs is 1.8V. The design without Johnson counter consumes a power of 1.179mW. It achieves a SQNR of 78.09 dB and SNR of 90.83 dB. The design with Johnson Counter consumes a power of 1.085mW. It achieves a SQNR of 99.27 dB and SNR of 100.16 dB.