Accelerating the Pre-Silicon Functional Verification Value Ramp Using Aspect Oriented Development

One of the key limiters to any verification effort is simulation speed. To be fair, digital RTL and gate-level simulators have a lot of work to do: they track signal transitions, (on four-level signals no less), through the equivalent of millions of logical gates. Meanwhile-paradoxically perhaps-verification code tends to be written in a procedural rather than a synthesizable fashion and does not need or use many of the signal level features provided by a typical digital simulator. The Universal Verification Methodology, known colloquially as UVM-implemented in System Verilog according to IEEE Standard 1800 in most sim-ulators-encourages modeling signal driven bus transactions as objects instantiated from classes. These objects contain the intent and content of the transaction, (e.g. address, direction, and data of a bus access), abstracting away signal level transitions. Passing these transaction objects from component to component as the lingua franca of verification, the language used to model what we should expect to see from the device under test, (DUT), limits the mechanics of signal interactions to a very thin layer at the interface between the DUT and the verification environment. With UVM abstracting verification away from signal level interactions, a new question naturally arises: Do we really need toggling clocks-perhaps thousands of times per created trans-action-propagating all the internal signals of our DUT, in order to simply test our verification environment? The answer is no. By removing the internals of the DUT-leaving only the signal ring that interfaces with the verification test bench-and reducing the clock speed if possible, simulation speed for verification environment testing can be increased by factors of 10, 100, or even 1000x depending on the design. In this paper, we'll show how to easily set up a verification environment from first principles so that it can be developed without the presence of the design under test. This not only reduces simulation times substantially, but can also be used to give the verification team a head start on the design team as a new project ramps towards kickoff. The methodology discussed provides more than just development speed. It can also be used to accelerate debug of the design and its associated verification environment. By removing the DUT, then pushing streams of transaction objects captured during simulation through the transaction-only verification environment, we can quickly determine if it is the DUT or the verification environment itself that's at fault. We'll review the concepts of transaction level modeling as it's proscribed in UVM. We'll show how to easily convert UVM agents, (or replace them if necessary), to shunt their signal based bus functional models, (BFMs), out of the picture. And finally, we'll show how to put these concepts and processes together to create verification code more efficiently so it's ready to go when or before the DUT is.