Observe and Regulate Memory Interference on MPSoC: a Practical Approach

The increasing deployment of AI-enabled cyber-physical applications in industrial automation, robotics, automotive, and avionics requires high computational power with strict timing guarantees. Heterogeneous multiprocessor systems-on-chip (MPSoCs) have emerged as a solution, integrating application cores, real-time cores, and accelerators to balance performance and energy efficiency. However, shared memory hierarchies adopted by MPSoC introduce contention, potentially jeopardizing the predictability of real-time tasks. To mitigate these memory-related issues, both hardware-based Quality-of-Service (QoS) and software-based memory monitoring and regulation strategies are available. However, in dependable and real-time contexts, QoS mechanisms are not always effective and, in general, configuring both hardware- and software-based regulation optimally remains challenging. This paper presents insights into MemPol, a recent software-based memory regulation approach, and its integration into Minerva Systems Architect, an industrial tool for managing memory contention in MPSoCs. Through a real-world use case, we demonstrate how systematic memory monitoring and regulation can preserve timing guarantees while maximizing system utilization.