Hybrid Optimization Algorithms for Dynamic and Static Power Reduction in Low-Power VLSI Circuits

In the context of Very Large Scale Integration (VLSI) design circuits power dissipation is another crucial requirement that needs to be minimized, especially with increasing growth in the need for power aware electronic systems. In this paper, a new generally applicable metaheuristic optimization approach utilising heuristic algorithms as well as machine-enforced models is proposed to for reducing, both dynamic and the steady-state power consumption in VLSI circuits. The proposed approach explicitly defines the optimization problem; it attempts to search for the best design through continuous and discrete Genetic Algorithms (GAs) and Particle Swarm Optimization (PSO). A number of heuristics simultaneously applied, such as SA for fine-tuning, improves global optima search. In addition, for dynamic control of the design parameters, Reinforcement Learning (RL) strategy is used to achieve adaptive optimization using the circuit feedback. Disconnecting active parts from the supply voltage as a subcategory of static techniques is incorporated with active techniques including clock disabling and DVFS. The feasibility is demonstrated by applying various tools and metrics by reducing dynamic power and static power by 37.5% and 40% respectively; average delay enhanced by 5.88%. The given findings reveal the application of this hybrid approach to be capable of not only achieving the strict energy demands of innovative applications but also offering competitive performance, making it a sound modeling platform for future VLSI designs.