A 1.8-V 95.8-dB SNDR Incremental Delta-Sigma ADC With Analog Noise Reduction Techniques for Sensor ROIC

A delta-sigma modulator (DSM)-based incremental analog-to-digital converter (ADC) is proposed for use in the readout integrated circuit of low-power high-resolution sensors. The proposed incremental delta-sigma ADC (IADC) consists of a second-order cascaded-of-integrators feedforward (CIFF) DSM with a successive approximation register (SAR) ADC-based 3-bit quantizer and a digital filter with a cascaded of integrators (CoI) structure. Design techniques to reduce analog noise such as flicker, thermal noise, and nonlinearities in the digital-to-analog converter (DAC) generated by a second-order CIFF DSM with a 3-bit quantizer are introduced and their effectiveness is verified by measured results of the DSM and IADC. In particular, the measurement results confirm that the improvement in the characterization of the flicker noise of the reference driver, including the band-gap reference for generating the reference voltage used in the feedback path of the DSM, determines the overall characterization of the DSM. Furthermore, the proposed low-power high-resolution IADC is implemented using a second-order CoI filter optimized for the designed DSM. The proposed IADC, implemented using a 180-nm CMOS process with a supply of 1.8 V, has an area of 0.296 mm2 and a power consumption of $124.5~\mu $ W. It has an input bandwidth of 500 Hz and a sampling rate of 1 kHz. To implement this, the DSM operating synchronized to an external clock with a frequency of 3.584 MHz has an oversampling ratio of 512 and a sampling rate of 512 kHz. When the differential analog input signal has a frequency of 100 Hz and an amplitude of 0.94 Vpp, the measured peak SNDR of the DSM is about 97.4 dB, while the measured SNDR of the IADC in this case is about 95.8 dB.