Design and Optimization of a 22 kV Super-Cascode Solid-State Switch for Oscillation Suppression and Synchronized Switching

In medium-voltage converters, achieving reliable medium-voltage switching is challenging due to the limited voltage ratings of commercially available switch devices. To overcome this limitation, the super-cascode structure is employed, enabling scalable high-voltage operation by connecting multiple low-voltage devices in series. In such a structure, balancing capacitor selection is critical for ensuring synchronized switching and minimizing oscillations, particularly during turn-on transients. Existing design approaches primarily focus on turn-off performance, often neglecting the effects of absolute capacitance values and turn-on dynamics. This paper presents a systematic analysis of capacitance selection in super-cascode switches, considering both capacitance offset and absolute values. The impact of these parameters on turn-on delay, voltage balancing, and oscillation suppression is investigated. A new balancing circuit is introduced to mitigate gate and drain-source oscillations, ensuring stable and synchronized operation across multiple devices. To validate the proposed approach, a 22 kV super-cascode switch using ten 3.3 kV SiC MOSFETs was developed and experimentally validated in a capacitor discharge circuit. Results demonstrate that optimized capacitance selection improves switching performance, suppresses oscillations, and extends the operational voltage range, providing a practical design framework for high-voltage solid-state switching applications.