Heterogeneous Integration of Advanced CMOS and Emerging Devices: Challenges and Solutions

The heterogeneous integration of advanced CMOS and emerging technology-based circuits as well as of chiplets at package level present promising avenues to meet the high computational intensity demands of AI applications, in particular due the strict constraints in terms of area, power consumption, and reliability. We classify heterogeneous integration at both the chip level, encompassing novel transistor types such as complementary FETs (CFETs) and novel devices, such as resistive memories, and at the packaging level, spanning from 2.5D to 3D and 5.5D approaches. In this context, the paper presents two case studies assuming the idea of vertical and horizontal integration at chip and packaging level. In more detail, case study I presents the design of vertically integrated inverters based on CFET and thin-film transistor (TFT), as well as the design of SRAM cells based on similar monolitic 3D integrations. In addition, case study II explores the main concepts and the state-of-the-art of heterogeneous integration of chiplets at package level. Quality and reliability aspects that are specific to the heterogeneous integration of advanced CMOS and emerging technologies are further discussed assuming a holistic approach based on circuits’ lifecycle phases. Finally, this paper provides insights and summarizes strategies to address some of these challenges, ensuring high quality and reliable integration for the next-generation of AI hardware.