Non-Uniform Error Correction for Hyperdimensional Computing Edge Accelerators

Brain-inspired Hyper Dimensional Computing (HDC) has attracted attention as a lightweight and efficient machine learning paradigm. It offers key advantages such as one-shot learning and resource efficiency, making it well-suited for resource-constrained edge devices. Although HDC has a certain degree of inherent fault tolerance, soft errors in associative memory can negatively impact performance, especially in safety-critical applications where reliability is crucial. While Error-Correcting Codes (ECC) are widely used for soft error correction in memory systems, their use often incurs substantial storage overhead, limiting their applicability in edge environments. In this paper, we propose an efficient, non-uniform fault correction framework that improves the robustness of HDC models while maintaining hardware performance efficiency. By leveraging absolute summation weight-based fault sensitivity analysis at the algorithmic level, our approach categorizes associative memory regions into distinct sensitivity groups, eliminating the need for time-consuming fault injection campaigns. We then apply tailored hardware protection strategies based on the fault sensitivity of regions, thereby optimizing fault correction with reduced hardware and memory overhead. This selective protection approach minimizes resource consumption and improves system resilience. The proposed approach is implemented on an FPGA and available as open source online.