Testing Functional Interfaces And Complex PADs Within Multi-Die Packages With IEEE P3405

Specialized external testers and custom load-boards cannot be used for testing die-to-die interfaces in a multi-chip in a package product as there is no access to the TX/RX buffers. On the other hand, small bump pitch allows for wafer test via sacrificial pads using a small set of signals. In this paper we discuss different techniques that can be used to test complex PADs and analog PHY interfaces. We show how these PADs with no synthesis libraries can be modeled for an EDA tool to automatically insert the wrapper logic. We also discuss how many of these ideas may be used by the IEEE P3405 standard, which would standardize testing of these interconnects.