Design and Implementation of a Multi-Channel Shared Cache

Facing the demand for parallel processing of massive data, multi-core and multi-threaded processors have become a new development trend. However, the traditional single-channel Cache faces many access conflicts and performance bottlenecks in multicore parallel computing. For this reason, this paper proposes a shareable multi-channel Cache architecture, which aims to optimize the data access efficiency, improve the Cache hit rate, and reduce the memory access latency, and assist the multicore multithreaded processor to break through the computational efficiency bottleneck. In this paper, a two-level Cache architecture is designed, and the main innovative work includes: (1) Crossbar-based 4-channel parallel access mechanism to realize multi-Bank concurrent access; (2) implementation of dynamic request splitting and merging mechanism to effectively reduce the number of L2 cache accesses; and (3) each read request can return multiple data consecutively, and the number of returned data is performed according to the number of specified at the time of request, with a maximum of 16 is supported. Simulation results show that the architecture supports efficient parallel accesses under read-intensive loads, which can effectively reduce the access latency; the logic synthesis is performed using Xilinx's Kintex-7 xc7k325tffg900-2 FPGA chip, and the synthesis report shows that the circuit can operate at a maximum speed of up to 289.1 MHz. The results of the study show that the architecture has a high degree of realizability and scalability and provides an effective caching solution for multi-core processing systems.