Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC

The additional N-well guard ring was often specified in the foundry's design rules to improve latch-up immunity of CMOS ICs. The impact of biasing the additional N -well guard ring on the latch-up immunity of a HV/LV mixed-voltage CMOS IC in a Bipolar-CMOS-DMOS (BCD) technology is investigated in this work. While intended to enhance latch-up immunity, an unexpected electrical overstress (EOS) failure is observed when the additional N -well guard ring is biased at low voltage during latch-up testing. Parasitic bipolar transistors between the highvoltage I/O devices and the additional N-well guard ring were activated to cause such an EOS failure. The effect of biasing the additional N-well guard rings on latch-up immunity is studied in detail through failure analysis.