Performance Evaluation of 55Nm SRAM Cell With Buried Power Rail and Backside Power Delivery Network

As the critical dimension of transistor and interconnect scaling continues, back-end metal resistance has increased significantly. Buried power rail (BPR) and backside power delivery network (BSPDN) have been proposed to alleviate metal distribution tension and optimize power, performance and area trade-offs. In this paper, BPR and BSPDN are introduced as power delivery structures in 55 nm SRAM cell. Simulation results demonstrate that BPR and BSPDN reduce bit line (BL) and word line (WL) capacitance by about 40 % and 12 %, respectively. These reductions lead to improvements in key performance metrics, including an increase in static noise margin (SNM) of 3.68 % at hold state and 3.17 % at read state, as well as a reduction in write delay by $\mathbf{7. 0 5 \%}$.