Multi-rate PAM4 Silicon Photonic Based Receiver Assembly with -10dBm iFEC Sensitivity at 226Gb/s/λ and 125mW/Ch CMOS TIA

We demonstrate a multi-rate PAM4 Silicon-photonic based receiver assembly that supports $226 \mathrm{~Gb} / \mathrm{s} / \lambda$, with -10 dBm iFEC OMA sensitivity, and $212 \mathrm{~Gb} / \mathrm{s} / \lambda$ and $106 \mathrm{~Gb} / \mathrm{s} / \lambda$ with 8.5 dBm and -11.5 dBm OMA KP4-FEC sensitivity, respectively. The CMOS TIA achieves $0.55 \mathrm{pJ} / \mathrm{b}$ power efficiency.