A Lightweight RISC-V Multi-Core Interaction Framework For Embedded Real-Time Applications

Multi-core architectures have been adopted to enhance computation capability in embedded real-time systems, yet the interaction between cores affects performance, hardware complexity, and utilization of the systems. Current approaches suffer from high complexity or limited flexibility. We present a lightweight task-based multi-core interaction framework compatible with RISC-V specifications, balancing complexity and flexibility. The method proposed relies on RISC-V Core Local Interrupt Controller (CLIC) with customized extensions on the standard AMBA bus offering fully programmable capability for task offloading/trigger and shared resource protection. Compared with the interconnect between TI’s C2000 Series cores and its Control Law Accelerator(CLA) co-processors, experiments show the method reduces more than 57% of the response cycles cost by multi-core task management, but only introduces overhead of less than 1% area of a dual-issue RISC-V core with 7-stage in-order pipeline.